The present invention relates to a method to reduce the gate leakage in metal oxide semiconductor capacitors formed in thin gate dielectric CMOS integrated circuits.
Capacitors are often required on integrated circuits to perform certain circuit functions. Although a number of different integrated circuit capacitors are possible, the most common type in use today is the metal oxide semiconductor (MOS) capacitor. In this device the gate dielectric acts as the capacitor dielectric. The plates of the capacitor are formed using the gate structure and the semiconductor substrate. A simple MOS capacitor is shown in FIG. 1. The semiconductor substrate 10 functions as one of the plates of the capacitor. The semiconductor can be doped either n-type or p-type. As shown in FIG. 1 the substrate can be connected to circuit ground 13. A dielectric layer 11 formed on the surface of the semiconductor substrate 10 functions as the capacitor dielectric. In the case of a silicon substrate the dielectric layer typically comprises silicon oxide or a silicon oxynitride. A gate structure 12 formed on the dielectric layer 11 functions as the second plate of the capacitor. Diffusion regions 16 will function as a source and sink form minority carriers required to form an inversion region beneath the gate 12 when the capacitor is biased in inversion. For a n-type substrate region 10 the diffusion regions will be p-type and for a p-type substrate the diffusion region 16 will be n-type. The diffusion regions 16 will also be connected to circuit ground 13. The capacitance value of the MOS capacitor is a function of the bias voltage Va 14 applied to the gate 12. The three well-defined states of the MOS capacitor are inversion, accumulation and depletion. These states are induced in the MOS capacitor through the application of various bias voltages Va to the gate 12. The states are described in relation to the applied voltage Va and two conditions of the MOS capacitor, flatband voltage VFB and threshold voltage VTH. Given a particular work function difference between the substrate 10 and the gate 12, the flatband voltage VFB is defined as that voltage which when applied to the gate 12 results in the silicon substrate beneath the gate being everywhere neutral. See MOS (Metal Oxide Semiconductor) Physics and Technology by E. H. Nocollian and J. R. Brews, page 41. The threshold voltage VTH is defined as that voltage which when applied to the gate 12 results in the maximum width of the depletion region 15. See Physics of Semiconductor Devices by S. Sze, page 373. Using the above definitions of VFB and VTH the three states of the MOS capacitor can be written in terms of the applied voltage as follows:
(a) Va less than VTH (inversion), VTH less than Va less than VFB (depletion), Va greater than VFB (accumulation) for an n-type substrate, and
(b) Va greater than VTH (inversion), VFB less than Va  less than VTH (depletion), Va less than VFB (accumulation) for a p-type substrate.
For a dielectric layer 11 with a dielectric permittivity of ∈ and thickness d the capacitance per unit area in strong accumulation and strong inversion is given by,
Cm=∈/d.
In the ideal case the capacitance value of the MOS capacitor is a maximum in strong inversion and strong accumulation and passes through a minimum as the MOS capacitor passes through depletion. Shown in FIG. 1 is a depletion region 15 formed in the semiconductor substrate 10 beneath the gate structure 12. For the case of an n-type substrate, the depletion region 15 is formed by applying a voltage Va less than VFB to the gate 12. For a p-type substrate a voltage Va greater than VFB applied to the gate 12 will form the depletion region 15. For a depletion region thickness of d1 and a silicon permittivity of ∈s the capacitance per unit area is given by,
C=CmCd/(Cm+Cd),
where Cd is given by ∈s/d1. Since d1 is a function of the applied bias voltage Va then the capacitance C is also a function of the applied bias voltage Va.
An unwanted component of a MOS capacitor is the leakage current IL that flows through the gate dielectric layer 11 when a bias voltage Va is applied to the gate 12. In general the leakage IL is a function of the bias voltage applied Va and the dielectric layer thickness d. The leakage current IL increases as the thickness of the dielectric layer d is reduced. It should be noted that the capacitance per unit area of the MOS capacitor increases as the dielectric layer thickness d is reduced.
There are many integrated circuit applications that utilize MOS capacitors. One such application is the phase lock loop (PLL). The PLL is used in many applications such as wireless telephones, receiver circuits, and network servers. A PLL is a circuit that causes a particular system to track with one another. More precisely, a PLL is a circuit synchronizing an output signal (generated by an oscillator) with a reference or input signal in frequency as well as in phase. In the synchronized or locked state, the phase error between the oscillator""s output signal and the reference signal is zero, or very small. If a phase error builds up, a control mechanism acts on the oscillator in such a way that the phase error is again reduced to a minimum. In such a control system the phase of the output signal is actually locked to the phase of the reference signal. A block diagram of a phase lock loop is shown in FIG. 2(a).
The PLL consists of three basic functional blocks: a voltage-controlled oscillator 30, a phase detector 20, and a loop filter 25. In general an input signal U1(t) is fed to the phase detector 20 along with the output signal U2(t) from the voltage controlled oscillator 30. The output signal from the phase detector Ud(t) is fed into the loop filter. In general the loop filter is a low pass filter with an output signal Uf(t) that comprises only low frequency or DC components. The output signal of the loop filter Uf(t) is fed into the voltage controlled oscillator 30. The output signal U2(t) of the voltage controlled oscillator 30 will depend on the input signal Uf(t). As stated above the loop filter 25 comprises a low pass filter. Such a low pass filter will comprise one or more capacitors often referred to as loop filter capacitors. An example of a low pass filter with a loop filter capacitor is shown in FIG. 2(b). Here the loop filter capacitor 50 is in the feedback loop of the amplifier 60 which has a resistance 40 connected to the input terminal. In integrated circuit implementations of a PLL circuit MOS capacitors are often used to form the loop filter capacitors.
In an integrated circuit PLL, MOS capacitors are often used to form the capacitors in the loop filter circuit. The dielectric layer thickness d used to form the capacitors is often the same layer used as the gate dielectric of the MOS transistors and is often less than 50A. The thin dielectric layer thickness d will result in increased leakage current IL through the capacitor. The proper operation of the PLL requires that the loop filter capacitors introduce very little leakage current into the circuit. As shown in FIG. 2(a), the output from the loop filter is fed into the voltage controlled oscillator. Leakage current introduced into the circuit through the loop filter capacitors will add to the input of the voltage controlled oscillator. The additional input signal to the voltage controlled oscillator can cause the PLL to drift and unlock. Using a second dielectric layer that is thicker than d can reduce the leakage current. However, there is significant cost associated with depositing and patterning such a layer for the capacitor. There is therefore a need for a method to reduce the leakage current in MOS capacitors without increasing the dielectric layer thickness d.
The instant invention is a method for reducing the leakage currents in MOS capacitors formed using thin gate dielectric layers. In a first embodiment the method comprises first determining the value of capacitor required in the integrated circuit. Since integrated circuits usually have an area constraint, a maximum allowable area AMAX for the MOS capacitor is then determined. The maximum allowable current IMAX that can pass through the MOS capacitor and not affect the proper operation of the circuit is determined. The method then involves determining a capacitor bias voltage Va such that the capacitor bias voltage Va results in a second capacitance value and a second capacitor current such that said second capacitance value is approximately equal to said first capacitance value and said second capacitor current is less than said maximum allowable current. The method is also constrained by determining the capacitor bias voltage Va that results in the MOS capacitor with an area A such that said area A is less than said maximum allowed area AMAX. The capacitor area A is determined from a capacitance voltage characteristic curve.
In a second embodiment the method comprises determining a value of total capacitance required for an integrated circuit. A capacitance value of a metal insulator metal capacitor is determined as well as a maximum allowable area AMAX for a MOS capacitor. The maximum allowable current IMAX for the MOS capacitor is determined; and a MOS capacitor bias voltage Va is found wherein the MOS capacitor bias voltage Va results in a MOS capacitor current and a MOS capacitor area such that the MOS capacitor current is less than said maximum allowable current and the MOS capacitor area is less than said maximum allowable area and combining the capacitance of said MOS capacitor and said metal insulator metal capacitor approximately equals the total capacitance.